S
somu.atluri
Guest
im synthesizing a code, and I want the tool to make use of 3-input gates...
but the tool is synthesizing with 2-input gates and inverters.
is there any command for RTL compiler to constrain and use 3-input gates.
Thanks in advance.
but the tool is synthesizing with 2-input gates and inverters.
is there any command for RTL compiler to constrain and use 3-input gates.
Thanks in advance.