[SOLVED] How to tell the synthesis tool to use a specific gate

[somu.atluri]

im synthesizing a code, and I want the tool to make use of 3-input gates...
but the tool is synthesizing with 2-input gates and inverters.

is there any command for RTL compiler to constrain and use 3-input gates.

Thanks in advance.

 

[eshwartt]

Hi Somu,

Answer is pretty simple...Put set_dont_use on 3 input gates in RTL compiler or DC. That's it...

Regards,
Eshwar

 

[somu.atluri]

hi eshwar,

i think i confused u with my question.

i want the tool to make use of 3 input gates where ever possible, and also use 2 input gates.

thanks anyway for the reply.

 

[gliss]

Maybe you can modify the library so that the 2 input gates are undesirable? Or read in the library and use the set_lib_attribute to modify the area or timing attribute of the 2 input cells you don't want so the tool won't use those gates for it's implementation.

 

[jaydip]

RC has a attribute called, set_prefered_cell or something similar .. search in command reference ... not sure about DC though ...

 

[somu.atluri]

I will try it out n reply. Thanks jaydip