How to Synthesize File handling VHDL code in xilinx

[rajavel.rv]

Hi guys, am writing a vhdl code with file reading and writing (image), how can am synthesize this code, in xilinx software, where the image file will be added, pls help as soon as possible,..


Thanks & Regrds,
Rajavel Ashokraj

 

[TrickyDicky]

You cannot. File IO is only for use in simulation.
You can use file IO to pre-load data into a memory though.

 

[sreevenkjan]

As Tricky mentioned you cannot synthesize and generate a bitstream. However you can save image (binary) in the RAMs of the FPGA and then read and write into them. This program can be synthesized and then can be checked and verified by using the chipscope tools of Xilinx. You should be careful that the memory is limited and you need to choose an image which can be stored in the FPGA. This method would not take much time.

However you can also use other methods where you can save the image in other external memory and use them for your task.

 

[rajavel.rv]

Thanks guys, am using memory to load the data, now its working.,,

Thanks & Regards
Rajavel Ashokraj