how to synthesis a verilog source into a gate level (generic) netlist in dc_shell?

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hcu

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Hello,

In cadence , there is a way to synthesize the source files in 3 steps like generic gatelevel representation like and, or ,not et., and then into actual cells avaialbe in library

commands are : syn -to_generic

syn -to_mapped

i want to know that, which command is used to synthesis a source into a generic gatelevel representaion in synopsys DC.

thanks
 

Just add <DC_installation_dir>/libraries/syn/gtech.db in your target_library and link_library and execute compile.
 

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