how to synchronization domain clk and asynchronous signal ?

[hgz]

double synchronizer

how to synchronization domain clk and asynchronous signal ? Thanks !

Bgs!
hgz

 

[wufengbo]

toggle synchronization

I think this article can help you.

 

[yeewang]

how to synchronize an asynchronous signal

double-sync, high-freq sampling, that's all.

 

[GoodMan]

clock domain crossing handshaking protocol

Hi,

How to design in different clock domain?

 

[hgz]

fourteen ways to fool your synchronizer pdf

Hi,
high freq sample is meas that if sample clock is lower than signal ,We can not syn the signal???
Thanks.

 

[akp494]

multi clock domain + grey code

This is a good article on the mentioned topic.
May be of some help to you.

 

[yeewang]

asynchronous sampling sync signals

Hi,
high freq sample is meas that if sample clock is lower than signal ,We can not syn the signal???
Thanks.

nope, transfer from higher clock domain to lower could also be performed if appropriate handshaking protocol is taken.

 

[hgz]

double synchronizer

Hi,yeewang:

Please more detail about this? Do you meas that if domain clk is unchanged, singal's sample freq is all ok if we have good handshake?
Thanks!

BGS!

 

[yeewang]

grey code in clock crossing domain

sure. the simplest scheme of handshaking is like the example below...
assert a request signal and make stable the data u wanna transfer in clock domain A;
sample the data until the reqA's assertion is detected in clock domain B;
assert a grant signal in clock domain B;
deassert the reqA when grantB detected in clk domain A;
deassert the grantB when reqA's deassertion detected in clock domain B;
done;
this is the simplest but low-efficient handshake scheme to transfer data from one clock domain to another, no matter what frequencies are.
try find some examples and try them urself.

 

[abc21]

fourteen ways to fool your synchronizer

where is the mirro site?

 

[chiente]

clock domain crossing handshake

The solution for crossing clock domain is depended on what's to sync,

Double sync works on most of case; use the signal after double sync INPUT to working clock domain, and double sync the OUTPUT to output
clock domain.

But some case you will need to calculate the throughput for data traffic
between two clock domain and decide whether need to use a FIFO(Buffer)
or not. If this was the case, just manage read and write port pointer (address) on appropriate clock domain. You can also use grey code on
read/write pointer increment/decrement to get arround meta state.

 

[satya]

clock domain crossing grey code

Hi all,
Doulble synchronization is not the perfect solution always..!!
consider a cycle-wide pulse generated in a high-frequency clock-domain and if you want to export it to a low-frequency domain..double sync doesnt work well from certain high-frequencies...

In that case toggle synchronization is the solution. This toggle synchronization works well for any clock-frequencies (unless two successive pulses come very close which will be limited by technology. for example in 0.18m 200Mhz is the highest frequency..)
some time back I posted an article "Fourteen ways to fool your synchronizer". Thats a very good article to know about the various synchronization methods and their drawbacks.

Thanks
Regards,
- satya

 

[wufengbo]

fourteen ways to fool your synchronizer

I think satya's method is the best one.This method can be found on Xilinx's website in detail.

 

[hgz]

async domain synchronize

Hi,satya:

Can you repost "Fourteen ways to fool your synchronizer" ? Thanks.

BGS!

 

[papyaki]

need for double synchronizers

Hi,

It is available here as power point file :

h**p://research.sun.com/async2003/Talks/Ginosar-ASYNC03-3.ppt

or as pdf file :

h**p://www.cs.utah.edu/classes/cs5830/papers/fool-sync.pdf

* = t

 

[alanray]

how double synchronization works

in sung group there are some good reference for async design

 

[omiga]

double synchronization for asynchronous signal

Different Clock domain is an important issue in IC design.

 

[tom123]

clk domain

for single bits signal, use two DFF to synchronize it.

for multi-bits signal, use two phase handshaking protocol

or use fifo.

how to synchronization domain clk and asynchronous signal ? Thanks !

Bgs!
hgz

 

[nemolee]

domain synchronization

If the clock is synchronous, you can use double click.
If the clock is asynchronous, you have to use FIFO arc.
This is my opinion.

 

[telantan]

assertion of the sampling clock

fifo , handshakeing
my opinion..