Hello everyone.
It's been a while since I worked on PLLs so I'm a little bit rusty on how to design one. I'm very familiar with the theory behind it (understand the function of each block; concepts like pull-in range, lock range, etc; why PFD is better; why charge pump is needed; how the loop filter order affects the stability; bla bla bla) but I'm having trouble getting started with my design.
I'm gonna have a very stable reference at 100 kHz, I need to lock into that frequency (and phase) and then store the filter's output, open the PLL loop and leave the VCO running at that frequency. I need to close the loop again every once in a while to compensate for any frequency/phase drift that might occur.
I will really appreciate if someone could give me a hand on guiding me on how to start. I don't need a design in particular, just ideas on, for example, which will be the most critical parameter I should set etc.
Thanks in advance,
diemilio