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How to start designing a PLL ?

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diemilio

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Hello everyone.

It's been a while since I worked on PLLs so I'm a little bit rusty on how to design one. I'm very familiar with the theory behind it (understand the function of each block; concepts like pull-in range, lock range, etc; why PFD is better; why charge pump is needed; how the loop filter order affects the stability; bla bla bla) but I'm having trouble getting started with my design.

I'm gonna have a very stable reference at 100 kHz, I need to lock into that frequency (and phase) and then store the filter's output, open the PLL loop and leave the VCO running at that frequency. I need to close the loop again every once in a while to compensate for any frequency/phase drift that might occur.

I will really appreciate if someone could give me a hand on guiding me on how to start. I don't need a design in particular, just ideas on, for example, which will be the most critical parameter I should set etc.

Thanks in advance,

diemilio
 

Re: PLL Design

OK... it seems I layout to broad of a problem, so I'm gonna give an update of what I've done so far and where I'm stuck right now... hopefully someone will be able to help me now that I'm narrowing the issue:

- I chose my central freq to be 150 kHz, fmin 50 kHz, fmax 200 kHz
- I don't need a freq divider
- Don't care about noise suppression cause I have a very stable reference all I want is for the VCO signal to be as similar as possible to it
- I'll be using PFD with charge pump
- The filter could be either first or second order (RC passive)

Now my question is: How do I choose the value of ωn??? I know that since I don't need noise suppression it doesn't have to be that small, but how do I set it then?? I will like to make it as large as possible, but I also know that by doing this the ripple at the output of the filter is gonna modulate the VCO's frequency bringing both stability and jitter issues. So how do I target for this value??

Thanks in advance,

diemilio
 

PLL Design

I don't understand your question vey well. What are you going to have? You want exactly the same frequency and phase as the stable source? Why not use the frequency reference? What you need is only a buffer.
 

Re: PLL Design

Cause the reference gets intentionally corrupted in both phase and frequency, so that's when the PLL loop is opened and the VCO is used to do the reference's job. The reference is then uncorrupted (for a short period of time) and the loop is closed again to recalibrate the VCO's freq and phase.

diemilo
 

Re: PLL Design

mind sharing how you chose ωn? when your fref is so small and ωn is conventionally 1/10 to 1/20 of fref, your loop filter components become prohibitively large.
 

PLL Design

Yes, I know, but I get to use MEMS caps which can go up to tens~hunders of nF, so my resistors came out to be of acceptable values
 

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