How to split a big SRAM memory into smaller ones?

[mech]

Can anyone tell me the overhead to split a big memory(SRAM) into two small memory(SRAM). For example, if I split a 2K SRAM into two 1K SRAM, I have twice the bandwidth. The how about the overhead, such as bist logic, ATE running time etc.

Thanks.

 

[mech]

Re: SRAM again

anyone can help?

 

[johnz]

Re: SRAM again

area of two 1k sram is bigger than 2k sram due to increase of line and column decode logic.

 

[dr_dft]

SRAM again

If the topology of the 2 instances of the 1k sram is the same as the 2k sram, theoretically the bist logic can be identical in both cases, and the test time would be identical.
If you split the 2k sram width-wise, where each 1k sram instance has half the data bits as the 2k sram, then you can drive the upper half of the bist data to one instance and the lower half to the other instance with no change in the bist controller. With some modification in the bist controller, you can test both 1k-srams simultaneously, saving some bist area.
If you split the 2k sram depth-wise, where each 1k sram instance has half the address space as the 2k sram, then you can use the upper bist address bit to select which 1k sram instance you are accessing with no change in the bist controller again. With some modification in the bist logic, you can test the 2 instances simultaneously, cutting down in ATE test time.

 

[Thomson]

Re: SRAM again

hi,dr_dft,
if i implement one system with three 512-byte SRAM as one method and with six 512-byte SRAM as the other method, then how about the testing cost? Does the latter method add much testing cost to the previous one? Here ignore the other logics' testing cost!


Thomson

 

[dr_dft]

SRAM again

Hi Thomson,
It really depends if you test the SRAMs serially or all SRAMs in parallel. If you test them serially, the test time will multiply by the number of instances. If you test them simultaneously, you need to add some extra BIST logic, but the extra logic is not too large.
Most BIST insertion tools these days (LogicVision, Mentor Graphics, etc.) allow you to build a BIST controller that can test all instances simultaneously, so if you can afford the extra logic, it will save you in test time, and hence test cost.

 

[Thomson]

Re: SRAM again

Hi Thomson,
It really depends if you test the SRAMs serially or all SRAMs in parallel. If you test them serially, the test time will multiply by the number of instances. If you test them simultaneously, you need to add some extra BIST logic, but the extra logic is not too large.
Most BIST insertion tools these days (LogicVision, Mentor Graphics, etc.) allow you to build a BIST controller that can test all instances simultaneously, so if you can afford the extra logic, it will save you in test time, and hence test cost.

Really appreciate your answer!
Where can i find the latest materials about this topic if i want to further study this topic?

Thomson

 

[dr_dft]

SRAM again

User manuals of LogicVision or Mentor Tools will show you how to set up the BIST insertion. Playing with the tools and talking to AEs is best way to get the latest.
Good luck.

 

[eeeraghu]

Re: SRAM again

depends on the read/write logic, also here when divided the data and address paths and even the control logic increases. so there is a use but instead using two rams use a single one by doubling the data path, i.e if it was 8 bit wide now use 16 bit.

regards