How to solve this warning?

[wonka]

Hi,

I use CPLD Global clock to divide internal clock paths for module working, but there is compiler warning:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

so, how I can avoid this warning? hoping for help!

 

[sachingorkhe]

Try to register your clock input details in the synthesis tool(Quartus-II).
Provide your clock details with minimum and maximum tolarable frequency and acceptable clock skew in the synthesis tool.

 

[wonka]

yes, after register the clock paths detail in synthesis tool, the warning is no display any more, thank you for your reply!!