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how to solve this $setup violation in gate-level simulation

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valxiao

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specify setup violation

hi,guys,
i encounter a problem with gate-level simulation, run in modelsim,it appear the following :
------------------------------------------------------------
r: ../../libs/modelsim_asic/fsc0g_d_sc.v(18445): $setup( negedge D &&& ~SEL:2841 ps, posedge CK:3 ns, 267 ps );
Time: 3 ns Iteration: 5 Instance: /../../../../../reg_coeff_data_reg_210_
------------------------------------------------------------

clk in testbench: forever # 3 clk clk <= ~clk;(6ns)
clk in synthesis: set clk_period 4.8ns*0.9
set clk_skew 0.4ns
...
and report_max_path is: 0.006ns
why still have violation with $setup for reg_coeff_data_reg_210_? thanks!

in sdf:
(CELL
(CELLTYPE "QDFZCGD")
(INSTANCE ../../reg_coeff_data_reg_210_)
(DELAY
(ABSOLUTE
(IOPATH CK Q (0.381:0.381:0.381) (0.346:0.346:0.346))
)
)
(TIMINGCHECK
(WIDTH (posedge CK) (0.258:0.258:0.258))
(WIDTH (negedge CK) (0.620:0.620:0.620))
(SETUP (posedge D) (posedge CK) (0.276:0.282:0.282))
(SETUP (negedge D) (posedge CK) (0.261:0.267:0.267))
(HOLD (posedge D) (posedge CK) (-0.099:-0.103:-0.103))
(HOLD (negedge D) (posedge CK) (-0.037:-0.039:-0.039))
(SETUP (posedge TD) (posedge CK) (0.421:0.421:0.421))
(SETUP (negedge TD) (posedge CK) (0.817:0.817:0.817))
(HOLD (posedge TD) (posedge CK) (-0.192:-0.192:-0.192))
(HOLD (negedge TD) (posedge CK) (-0.155:-0.155:-0.155))
(SETUP (posedge SEL) (posedge CK) (0.783:0.783:0.783))
(SETUP (negedge SEL) (posedge CK) (0.353:0.353:0.353))
(HOLD (posedge SEL) (posedge CK) (-0.128:-0.128:-0.128))
(HOLD (negedge SEL) (posedge CK) (-0.034:-0.034:-0.034))
)
)


in stand-cell
module QDFZCGD(Q, D, TD, CK, SEL);
reg flag; // Notifier flag
output Q;
input D, CK, TD, SEL;
supply1 vcc;

wire d_CK, d_D, d_TD, d_SEL;

//Function Block
`protect
buf g3(Q, qt);
dffrsb_udp g2(qt, d1, d_CK, vcc, vcc, flag );
mux2_udp g4(d1, d_D, d_TD, d_SEL );

//Specify Block
specify

// Module Path Delay
(posedge CK *> (Q :1'bx)) = (10.68:16.82:30.00, 11.19:17.49:31.13);

// Setup and Hold Time
specparam setup_D_CK = 9.30;
specparam hold_D_CK = 0.00;
specparam setup_TD_CK = 10.30;
specparam hold_TD_CK = 0.00;
specparam setup_SEL_CK = 8.60;
specparam hold_SEL_CK = 0.00;
$setuphold(posedge CK, posedge D &&& ~SEL, 7.91:13.35:25.21, -2.94:-4.93:-8.41, flag,,,d_CK, d_D);
$setuphold(posedge CK, negedge D &&& ~SEL, 6.55:11.99:24.10, -1.46:-2.09:-2.87, flag,,,d_CK, d_D);
$setuphold(posedge CK, posedge TD &&& SEL, 10.87:18.28:36.31, -4.92:-8.14:-14.82, flag,,,d_CK, d_TD);
$setuphold(posedge CK, negedge TD &&& SEL, 22.09:38.87:79.21, -7.51:-9.99:-14.21, flag,,,d_CK, d_TD);
$setuphold(posedge CK, posedge SEL, 22.58:38.87:78.10, -4.92:-7.64:-13.35, flag,,,d_CK, d_SEL);
$setuphold(posedge CK, negedge SEL, 11.61:19.14:35.81, -1.59:-2.59:-3.36, flag,,,d_CK, d_SEL);

// Minimum Pulse Width
specparam mpw_pos_CK = 15.64;
specparam mpw_neg_CK = 17.40;
$width(posedge CK, 6.87:12.53:25.83, 0, flag);
$width(negedge CK, 17.95:30.51:62.04, 0, flag);
endspecify
`endprotect
endmodule
`endcelldefine

when synthesis ,i have used "set_fix_hold clk"
 

love2read

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error: $setup( posedge d modelsim

You should run STA tool to check the violation.
 

linuxluo

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standard delay format setup violation

hi,
first , use STA to check if timing is met.
if not and you still want to go on, pls manually modify sdf file
 

Nandy

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setuphold (posedge d) (posedge clk)

The violation happens at the first clock rising edge. Looks you have some problem in testbench setup. How do you drive the input pins to the design?
Normally the best way to debug this kind of problem is to dump waveform and check the time point when violation happens.
The GUI netlist debug tool GOF from NanDigits is very handy in debug gate-level netlist. It can isolate the violation cell and trace the inputs of the cell until the root of violation.
Take a loot at partial schematic in isolating logic
https://www.nandigits.com/partial_schematic.htm
Also it has interface to Gtkwave and Novas nWave.
https://www.nandigits.com/waveform_restore.htm

Hope this helps.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode
 
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leeenghan

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gate level simulation setup

Hi,

The setup reported by the tool said that when the data changed at 2.841ns, and the clock rise at 3ns. As the FF has 0.267ns setup requirement, there is a (2.841+0.267 - 3) setup violatoin.

Base on you description, it seem that the clock should rise at 6ns, and not a 3ns.

Regards,
Eng Han
 
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