Here's my understanding of the question hfly47 is asking:
hfly47 is prototyping an ASIC design, and has broken it into two separate modules for the sake of debugging. Each module will be programmed onto a unique FPGA. The problem hfly47 is running into is that he has more signals that he can physically communicate between the two FPGAs because of IO limitations.
kvingle makes a good point, but I think he misinterpreted that the "modules" are living on separate FPGAs. FvM is spot on... citing a need for clarification:
What is your reason for using two FPGAs hfly47? Do you have insufficient logic elements when using just a single part? Can you tell us what devices you're working with?