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Logicdevv said:Hi,
Can you allobrate you problem in detail..
usually depends upon your module(block) of design, you allocate/share the pins of FPGA..
to test a particular block
Logicdevv_co_uk
hfly47 said:I mean that if how the design is partitioned has been determined (that is the partition will keep unchanged), and the number of logical pins between any two partitioned modules is larger than the number of physical pins between their corresponding FPGAs, how to pass the value of logic pins with less physical pins with no functional timing changed?
kvingle said:hfly47 said:I mean that if how the design is partitioned has been determined (that is the partition will keep unchanged), and the number of logical pins between any two partitioned modules is larger than the number of physical pins between their corresponding FPGAs, how to pass the value of logic pins with less physical pins with no functional timing changed?
presuming your FPGA design is broken down in to modules.....(If that is what you are referring as modules)Why you want use physical pins for communication between these modules when both modules are INSIDE the FPGA
kgroll said:Here's my understanding of the question hfly47 is asking:
hfly47 is prototyping an ASIC design, and has broken it into two separate modules for the sake of debugging. Each module will be programmed onto a unique FPGA. The problem hfly47 is running into is that he has more signals that he can physically communicate between the two FPGAs because of IO limitations.
kvingle makes a good point, but I think he misinterpreted that the "modules" are living on separate FPGAs. FvM is spot on... citing a need for clarification:
What is your reason for using two FPGAs hfly47? Do you have insufficient logic elements when using just a single part? Can you tell us what devices you're working with?
rainrhythm said:Please try TDM (Time Division Multiplexing), Share multiple pins in single pin.
However, the frequency will be very low.
Some article may help you...
https://www.design-reuse.com/articl...timing-closure-challenges-with-solutions.html
rainrhythm said:Please try TDM (Time Division Multiplexing), Share multiple pins in single pin.
However, the frequency will be very low.
Some article may help you...
https://www.design-reuse.com/articl...timing-closure-challenges-with-solutions.html