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How to solve pin limitation when prototyping with FPGAs?

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hfly47

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Hi,

Pin limitation is indeed a problem when prototyping ASIC with FPGAs.
Is there a good way to solve it?
Thank you~
 

Logicdevv

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Hi,
Can you allobrate you problem in detail..

usually depends upon your module(block) of design, you allocate/share the pins of FPGA..
to test a particular block

Logicdevv_co_uk
 

hfly47

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Hi, Logicdevv

I mean that if how the design is partitioned has been determined (that is the partition will keep unchanged), and the number of logical pins between any two partitioned modules is larger than the number of physical pins between their corresponding FPGAs, how to pass the value of logic pins with less physical pins with no functional timing changed? Timeplexing?
Thanks

Logicdevv said:
Hi,
Can you allobrate you problem in detail..

usually depends upon your module(block) of design, you allocate/share the pins of FPGA..
to test a particular block

Logicdevv_co_uk
 

kvingle

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hfly47 said:
I mean that if how the design is partitioned has been determined (that is the partition will keep unchanged), and the number of logical pins between any two partitioned modules is larger than the number of physical pins between their corresponding FPGAs, how to pass the value of logic pins with less physical pins with no functional timing changed?
presuming your FPGA design is broken down in to modules.....(If that is what you are referring as modules)Why you want use physical pins for communication between these modules when both modules are INSIDE the FPGA
 

FvM

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I know, that it has been necessary in some cases to split large ASIC emulations into multiple FPGAs when a single FPGA
hasn't sufficient logic elements. Of course, this method is rather limted in terms of achievable clock speed. I would expect
that today most emulation work could be performed with a single FPGA.

Unfortunately, the problem hasn't been presented clearly yet.

If it's actually about needing multiple FPGAs due to resource limitations, the functional timing most likely can't be
kept by using individual pins for interconnect. Adding multiplexers completely cancels a realistic simulation.
 

hfly47

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Sorry for my confusing description.

Suppose that the design has been partitioned into module A and module B (for debugging ease), and each one of them will be mapped into an FPGA. But the number of the physical pins bwtween two FPGAs is smaller than the number of signals (in bit) between module A and B.
Then, how to transfer those signals with less physical pins, without timing changed? Does timeplexing can help?

kvingle said:
hfly47 said:
I mean that if how the design is partitioned has been determined (that is the partition will keep unchanged), and the number of logical pins between any two partitioned modules is larger than the number of physical pins between their corresponding FPGAs, how to pass the value of logic pins with less physical pins with no functional timing changed?
presuming your FPGA design is broken down in to modules.....(If that is what you are referring as modules)Why you want use physical pins for communication between these modules when both modules are INSIDE the FPGA
 

kgroll

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Here's my understanding of the question hfly47 is asking:

hfly47 is prototyping an ASIC design, and has broken it into two separate modules for the sake of debugging. Each module will be programmed onto a unique FPGA. The problem hfly47 is running into is that he has more signals that he can physically communicate between the two FPGAs because of IO limitations.

kvingle makes a good point, but I think he misinterpreted that the "modules" are living on separate FPGAs. FvM is spot on... citing a need for clarification:

What is your reason for using two FPGAs hfly47? Do you have insufficient logic elements when using just a single part? Can you tell us what devices you're working with?
 

hfly47

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Hi, kgroll

Single FPGA has no sufficient resources for mapping our design. The device we are using is Xilinx XC5VLX330-1-FF1760.

kgroll said:
Here's my understanding of the question hfly47 is asking:

hfly47 is prototyping an ASIC design, and has broken it into two separate modules for the sake of debugging. Each module will be programmed onto a unique FPGA. The problem hfly47 is running into is that he has more signals that he can physically communicate between the two FPGAs because of IO limitations.

kvingle makes a good point, but I think he misinterpreted that the "modules" are living on separate FPGAs. FvM is spot on... citing a need for clarification:

What is your reason for using two FPGAs hfly47? Do you have insufficient logic elements when using just a single part? Can you tell us what devices you're working with?
 

hfly47

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