How to solve hundreds of setup violations of paths in pre-layout STA?

[engr]

hi ,

i have ran PT on prelayout netlist, i have seen lot of setup violations in 100s of paths? whats my next step,since its huge no paths, i cant sit and see each and everypath.

please suggest , how should i approch now

thanks in advance

 

[shitansh]

Re: pre-layout STA

Fist of all try to see is there any common thing with in these group of signals. Like setup violations is flags due to what reason? if one of reason is clock skew then due to that on some group of path same setup violation may occure.

You need to resolve only clock skew and then set of violations will disappear. this is one of the approach.

Bottom of the line first analyze report properly and then try to work out.

HTH

 

[lostinxlation]

Re: pre-layout STA

If you didn't see violations during synthesis, but see viols with PT, the most probable cause is you forgot to take care of high fan out nets in PT while you set them as ideal net on synthesis.

 

[engr]

Re: pre-layout STA

Hi lostinxlation,

Thanks,

Could you please let me know, what should i do on these high fanout signals for pre-layouts runs with pt?

 

[shitansh]

Re: pre-layout STA

hi,

First thing you can do synthesis with Logic Duplication, after that also if you see violations then perhaps you can guide DC to use higher size drive cell.

Let's some one puts more light on this.

HTH

 

[lostinxlation]

Re: pre-layout STA

Hi lostinxlation,

Thanks,

Could you please let me know, what should i do on these high fanout signals for pre-layouts runs with pt?

You can set them false paths with set_false_path command for pre-layout STA if the affected paths aren't timingwise important(like reset signals and scan related signals). Also make sure to treat the clocks as ideal.

 

[shitansh]

Re: pre-layout STA

You can set them false paths with set_false_path command for pre-layout STA if the affected paths aren't timingwise important(like reset signals and scan related signals). Also make sure to treat the clocks as ideal.

If there is setup violations due to high fanout and similar reason and then also if you are going to ignore it by setting false path, then you end up with your chip died.

BOttom of line, be careful to give constraint to your design. Other wise you will going to make tool fool and .........

 

[lostinxlation]

Re: pre-layout STA

If there is setup violations due to high fanout and similar reason and then also if you are going to ignore it by setting false path, then you end up with your chip died.

BOttom of line, be careful to give constraint to your design. Other wise you will going to make tool fool and .........

This is a prelayout STA. There is no clock tree, possibly no reset tree etc. and setting false paths to those high fanout nets is commonly done at this design stage.