sasidhar442
Newbie level 3
how i simulate vhdl testbench in modelsim simulator?.. please help critically needed..........
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Testbench code is not for synthesis (i.e. Quartus), it is only for simulation (i.e. Modelsim...like you asked for in your original post).@davidryv
In the given testbench code , when I compiled it in quartusII it gave error:"Wait Statement must contain condition clause with UNTIL keyword"
You do compile it...with Modelsim, not Quartus. Then you simulate it...again, with Modelsim, not Quartus.@k-j
but for simulation shouldn't we compile the code and check for errors??
thanks for the help