How to simulate the loopwidth of PLL?

[icsoul]

In behavior level or transistor level.


Thanks!~

 

[LvW]

Hi,

as a simple method (and a rough but good) estimate you can simulate the transfer function of the linear PLL modell (which applies only for phase inputs/outputs in locked condition and small phase deviations).
Then, the (one-sided) Bandwidth is more or less equal to the pole resp. natural frequency of the loop, which is primarily determined by the loop filter and the DC loop gain. (Formulas are also available in relevant textbooks).

 

[icsoul]

Hi, LvW

What about transistor level?

 

[jecyhale]

In behavior level or transistor level.


Thanks!~

 

[LvW]

Hi icsoul,

one alternative to find a value for the loop BW by simulation on transistor level is to use frequency modulation.
Most simulators provide a signal source with FM .
You should increase the frequency deviation caused by the FM process slowly step by step and watch the VCO control signal (which should contain the demodulated signal).
When the frequency deviation reaches the loop bandwidth the demodulated signal begins to change its amplitude.
LvW

 

[rfsystem]

Because the loop bandwidth is an AC definition and the basic PLL operation time-discrete, value continuous with special feature that the PFD convert phase difference into values.

So you have to separate analyze the loop:

1. Determine the KVCO, simulate VCO at two different VCO voltages
2. Determine the KCHP, is simply the pulse current level

3. Simulate the transfer function

ChargePumpCurrent -> VCOVoltage

Plot the transfer function of 3. and add the (KVCO/s)*KCHP/(2*pi*DIV) as a scale factor.

Where the loop gain hit the 0dB is the BW.

 

[icsoul]

Because the loop bandwidth is an AC definition and the basic PLL operation time-discrete, value continuous with special feature that the PFD convert phase difference into values.

So you have to separate analyze the loop:

1. Determine the KVCO, simulate VCO at two different VCO voltages
2. Determine the KCHP, is simply the pulse current level

3. Simulate the transfer function

ChargePumpCurrent -> VCOVoltage

Plot the transfer function of 3. and add the (KVCO/s)*KCHP/(2*pi*DIV) as a scale factor.

Where the loop gain hit the 0dB is the BW.

Hi, rfsystem

Thank you very much!
Your answer is very helpful, it gives me some ideas at least.

I want to affirm some questions:

1. According your point, the PLL cannot be simulated in a whole? The only method is to simulate the building blocks respectively and calculate the bandwidth?

2. Some books use the 3dB bandwith of the close loop, but the others use the unity gain bandwidth of the open loop as the "loop bandwithd". Now I'm confused. What is the exactly mean of loop bandwidth?

3. Could you demonstrate "time-discrete, value continuous " in more detail?

Added after 15 minutes:

Hi icsoul,

one alternative to find a value for the loop BW by simulation on transistor level is to use frequency modulation.
Most simulators provide a signal source with FM .
You should increase the frequency deviation caused by the FM process slowly step by step and watch the VCO control signal (which should contain the demodulated signal).
When the frequency deviation reaches the loop bandwidth the demodulated signal begins to change its amplitude.
LvW

Hi, LvW

Thanks for your reply.

But I think your method will not work. Did you get the loop bandwidth with your method ever?

According my understanding, the AC analysis is face to special operation point. But I cannot give a correct operation point to ensure the PLL is locked when AC analysis is done.

 

[LvW]

Quote:But I think your method will not work. Did you get the loop bandwidth with your method ever?

Of course, I got the BW by using this method; otherwise I would´nt it propose.

Quote: According my understanding, the AC analysis is face to special operation point. But I cannot give a correct operation point to ensure the PLL is locked when AC analysis is done.

I did not mention an AC analysis; instead it is a pure simulation vs. time.

Comment to rfsystem: ..... and the basic PLL operation time-discrete.......

I do not understand why the basic PLL operation should be time-discrete. Did we talk about digital PLL´s ???

 

[icsoul]

Quote:But I think your method will not work. Did you get the loop bandwidth with your method ever?

Of course, I got the BW by using this method; otherwise I would´nt it propose.

Quote: According my understanding, the AC analysis is face to special operation point. But I cannot give a correct operation point to ensure the PLL is locked when AC analysis is done.

I did not mention an AC analysis; instead it is a pure simulation vs. time.

But how can I get the frequency response curve of the PLL system without AC analysis, but transient analysis?

 

[LvW]

As I have mentioned it in my reply May 9th:

Increase the frequency deviation step by step......
Of course, you should start at reasonable values.

By the way: which kind of PD do you use ?

 

[icsoul]

As I have mentioned it in my reply May 9th:

Increase the frequency deviation step by step......
Of course, you should start at reasonable values.

By the way: which kind of PD do you use ?

Oh, I got your point. I'll try it.

I use PFD(2 DFFs)+ Charge Pump.

Thanks again!~

 

[LvW]

Hello ICSOUL,

of course, you can try to find the loop BW also using an ac analysis.
However, in this case all blocks of your PLL must be linearized before.
Than, this holds only for the locked condition and for input/output signals which are phases.

Normally, this is not a problem - as far as I know - for all units, except the PD.

If you have a simple multiplier PD it is replaced in the linear model by an simple adder. But I don´t know what the linearized model is for the charge pump.

Do you have a linear charge pump model regarding phase inputs ?

LvW

 

[rillyxue]

you can run simulation of lock or setting time of pll , and compute loop filter bandwidth from lock time.

 

[icsoul]

Hello ICSOUL,

of course, you can try to find the loop BW also using an ac analysis.
However, in this case all blocks of your PLL must be linearized before.
Than, this holds only for the locked condition and for input/output signals which are phases.

Normally, this is not a problem - as far as I know - for all units, except the PD.

If you have a simple multiplier PD it is replaced in the linear model by an simple adder. But I don´t know what the linearized model is for the charge pump.

Do you have a linear charge pump model regarding phase inputs ?

LvW

I do AC analysis for the PLL,but an error result is gotten. I think the reason is that the pll system must be in lock state when AC analysis is done. But I don't know how to get this state( transistor level).

Sorry, I have no the linear model of CP.

I'm not familiar with PLL simulation for so many performance parameter. So I come here to get help.

 

[LvW]

Quote: I do AC analysis for the PLL,but an error result is gotten. I think the reason is that the pll system must be in lock state when AC analysis is done. But I don't know how to get this state( transistor level).


Since the PD (in your case: CP) is a nonlinear device an ac analysis cannot lead to reasonable results.
The best way is to create a model of the PLL with linear blocks.

In the attached diagram a linear model is shown for a multiplier type phase detector.

 

[icsoul]

LvW:

You are very helpful, thanks!!

I always want to simulatie the PLL in transistor level.

Do you think this is practical for charge pump PLL?