Nov 7, 2007 #1 rakesh_aadhimoolam Full Member level 4 Joined Mar 14, 2006 Messages 206 Helped 19 Reputation 38 Reaction score 2 Trophy points 1,298 Activity points 2,751 Hi.... Yesterday i generated a counter in Xilinx Core generator... How to simulate the same...is there any test bench model for that in Xilinx Itself... Thanks
Hi.... Yesterday i generated a counter in Xilinx Core generator... How to simulate the same...is there any test bench model for that in Xilinx Itself... Thanks
Nov 9, 2007 #2 L ls000rhb Full Member level 3 Joined Jun 17, 2005 Messages 185 Helped 7 Reputation 14 Reaction score 1 Trophy points 1,298 Activity points 2,425 Project/New Sourece/Testbench WaveForm BR. ls000rhb
Dec 21, 2007 #3 K kuseraj Newbie level 5 Joined May 23, 2007 Messages 9 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,325 hai, just give the inputs from test bench an simulate it with regs, kr
Jan 8, 2008 #4 A amittewarii Junior Member level 1 Joined May 15, 2006 Messages 15 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,377 Dear Rakesh , Perform two task for simulating it : 1. U need to write ur own testbench 2. Do include the instances from unisims or simprims library which have been instantiated in ur generated design . For linux the hierarchy for unisims goes as : Xilinx/verilog/src/unisims copy the instantiated models to ur simulations directory or give path to above directory in ur filelist . cheers , Amit Tewarii
Dear Rakesh , Perform two task for simulating it : 1. U need to write ur own testbench 2. Do include the instances from unisims or simprims library which have been instantiated in ur generated design . For linux the hierarchy for unisims goes as : Xilinx/verilog/src/unisims copy the instantiated models to ur simulations directory or give path to above directory in ur filelist . cheers , Amit Tewarii