How to simulate Core Generated Model of Xilinx....?

[rakesh_aadhimoolam]

Hi....

Yesterday i generated a counter in Xilinx Core generator...

How to simulate the same...is there any test bench model for that in Xilinx Itself...

Thanks

 

[ls000rhb]

Project/New Sourece/Testbench WaveForm

BR.
ls000rhb

 

[kuseraj]

hai,
just give the inputs from test bench an simulate it

with regs,
kr

 

[amittewarii]

Dear Rakesh ,
Perform two task for simulating it :

1. U need to write ur own testbench
2. Do include the instances from unisims or simprims library which have been instantiated in ur generated design .

For linux the hierarchy for unisims goes as :

Xilinx/verilog/src/unisims
copy the instantiated models to ur simulations directory or give path to above directory in ur filelist .

cheers ,
Amit Tewarii