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Hi! I want to simulate AND operation using MOSFET's in Proteus. I have attached a screenshot of the design. But I'm not getting the necessary output. (when A and B is logic 1 Z should be logic 1) What is the mistake?
- copy a CMOS AND gate from literature
- derive the circuit respectively correct a wrong approach based on known behaviour of MOS transistors
Presently I'm under the impression that you have difficulties with either method. Please compare your circuit (without the inverter) little-by-little with the below shown copy from an ASIC library. Pay attention to the letters "N" and "P" and the position of source terminals.
To be honest, the position of source terminals doesn't actually matter because source and drain are interchangeable. But the MOS transistors used in your simulation have source and substrat terminal shorted against each other, and the substrate connection definitely matters. In a standard CMOS process, all N substrates are connected to GND and all P substrates to VDD. To model it exactly, you would use transistor symbols with separate substrate connection.