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How to simplify this code (verilog) ?

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agrey

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verilog always @ (posedge clk or posedge )

Dear all,
I'm writing a 8-bit register with different reset bit. I try to rewite it by using for loop expression but the dc synthesis result is not the same as these two code.
Could someone kindly help me on it ? Thanks a lot.

Below is my rtl code:
module test(sw_rst, wr_en, out, data ,rst, clk);

input wr_en; // write enable
input rst; // global reset
input clk;
input [7:0] sw_rst; // software reset
input [7:0] data;

output [7:0] out;

reg [7:0] out;

always @(posedge clk or posedge rst)
if (rst) out[0] <= #1 1'b0;
else if (sw_rst[0]) out[0] <= #1 1'b0;
else if (wr_en) out[0] <= #1 data[0];

always @(posedge clk or posedge rst)
if (rst) out[1] <= #1 1'b0;
else if (sw_rst[1]) out[1] <= #1 1'b0;
else if (wr_en) out[1] <= #1 data[1];

always @(posedge clk or posedge rst)
if (rst) out[2] <= #1 1'b0;
else if (sw_rst[2]) out[2] <= #1 1'b0;
else if (wr_en) out[2] <= #1 data[2];

always @(posedge clk or posedge rst)
if (rst) out[3] <= #1 1'b0;
else if (sw_rst[3]) out[3] <= #1 1'b0;
else if (wr_en) out[3] <= #1 data[3];

always @(posedge clk or posedge rst)
if (rst) out[4] <= #1 1'b0;
else if (sw_rst[4]) out[4] <= #1 1'b0;
else if (wr_en) out[4] <= #1 data[4];

always @(posedge clk or posedge rst)
if (rst) out[5] <= #1 1'b0;
else if (sw_rst[5]) out[5] <= #1 1'b0;
else if (wr_en) out[5] <= #1 data[5];

always @(posedge clk or posedge rst)
if (rst) out[6] <= #1 1'b0;
else if (sw_rst[6]) out[6] <= #1 1'b0;
else if (wr_en) out[6] <= #1 data[6];


always @(posedge clk or posedge rst)
if (rst) out[7] <= #1 1'b0;
else if (sw_rst[7]) out[7] <= #1 1'b0;
else if (wr_en) out[7] <= #1 data[7];

endmodule
 

dcreddy1980

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Code:
module test(sw_rst, wr_en, data_out, data_in ,rst, clk);

input wr_en; // write enable
input rst; // global reset
input clk;
input [7:0] sw_rst; // software reset
input [7:0] data_in;

output [7:0] data_out;

wire [7:0] data_out;

genvar i;
generate
for(i=0;i< 8;i=i+1)
begin
flop flop_inst 
(
                        .clk(clk),
                        .rst(rst),
                        .sw_rst(sw_rst[i]),
                        .wr_en(wr_en),
                        .data_in(data_in[i]),
                        .data_out(data_out[i]) 
);

end
endgenerate

endmodule

module flop(sw_rst, wr_en, data_out, data_in ,rst, clk);

input wr_en; // write enable
input rst; // global reset
input clk;
input sw_rst; // software reset
input data_in;

output data_out;

reg data_out;

always @(posedge clk or posedge rst)
if (rst) data_out <= #1 1'b0;
else if (sw_rst) data_out <= #1 1'b0;
else if (wr_en) data_out <= #1 data_in; 

endmodule
 

    agrey

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agrey

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Dear dcreddy1980:

Thanks your help . But I need to modify it to run dc. ^^

Original :
for(i=0;i< 8;i=i+1)
begin
flop flop_inst
.........

Revised:
for(i=0;i< 8;i=i+1)
begin : flop_name
flop flop_inst
.........
 

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