[SOLVED] How to shift 4 bits by 4 bits in 16-bit output data?

Status
Not open for further replies.
J

jianhuachews

Member level 2
Joined
Jun 7, 2011
Messages
50
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,662
Hi guys, how do i go about shift 4 bit by 4 bits in a 16-bit output data?

for example i have "0000000000000000" then i can only send in 4 bits at a time (lets say i send in "1111" the first time and "1010" the second time) so my output should show something like "0000000000000000" => "0000000000001111" => "0000000011111010"

any guidance?
 

Re: 16-bit shifting vhdl

output_data(15 downto 4) <= output_data(11 downto 0);
output_data(3 downto 0) <= new 4 bit data;

these two statements should be clocked..
 

Re: 16-bit shifting vhdl

Assumind a
my_vector std_logic_vector(15 downto 0)

my_vector<= my_vector(11 downto 0) & "1111"; --shift four bits left and insert the new value in the lower four bits
my_vector<= my_vector(11 downto 0) & "1010";

Alex
 

Re: 16-bit shifting vhdl

Hi vipin. I took your advice and created a testbench too. i checked the waveform and it works the way i want. But xilinx ise gave me this error

Any suggestions?

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity key_decode is
port ( 
        key_out : out std_logic_vector(15 downto 0);
        enable1 : out std_logic;
        row_indata, column_in : in std_logic_vector(3 downto 0);
        clk1 : in std_logic
        );
end key_decode;

architecture Behavioral of key_decode is
signal key_data: std_logic_vector(3 downto 0);
signal key_out_s: std_logic_vector(15 downto 0);
begin
  
enable1 <= '0' when row_indata = "1111" else 
            '1';
            
process(clk1)
begin
          if(clk1'event and clk1 ='1') then
				key_out_s(15 downto 4) <= key_out_s(11 downto 0);
            key_out_s(3 downto 0) <= key_data;
           elsif(row_indata="0111" and column_in="0111") then
                key_data<="0001";  -- binary for 1
           elsif(row_indata="0111" and column_in="1011") then
                key_data<="0010"; -- binary for 2
           elsif(row_indata="0111" and column_in="1101") then
                key_data<="0011"; -- binary for 3
           elsif(row_indata="0111" and column_in="1110") then
                key_data<="1111"; -- binary for F
           elsif(row_indata="1011" and column_in="0111") then
                key_data<="0100"; -- binary for 4
           elsif(row_indata="1011" and column_in="1011") then
                key_data<="0101"; -- binary for 5
           elsif(row_indata="1011" and column_in="1101") then
                key_data<="0110"; -- binary for 6
           elsif(row_indata="1011" and column_in="1110") then
                key_data<="1110"; -- binary for E
           elsif(row_indata="1101" and column_in="0111") then
                key_data<="0111"; -- binary for 7
           elsif(row_indata="1101" and column_in="1011") then
                key_data<="1000"; -- binary for 8
           elsif(row_indata="1101" and column_in="1101") then
                key_data<="1001"; -- binary for 9
           elsif(row_indata="1101" and column_in="1110") then
                key_data<="1101"; -- binary for D
           elsif(row_indata="1110" and column_in="0111") then
                key_data<="1010"; -- binary for A
           elsif(row_indata="1110" and column_in="1011") then
                key_data<="0000"; -- binary for 0
           elsif(row_indata="1110" and column_in="1101") then
                key_data<="1011"; -- binary for B
           elsif(row_indata="1110" and column_in="1110") then
                key_data<="1100"; -- binary for C  
           
        end if;
end process;

       key_out <= key_out_s;

end Behavioral;
 

Re: 16-bit shifting vhdl


use different if statement for clock and row_indata , column_in

dont combine within one "IF" statement

that error is because you are assigning both in positive and negative edge of clock...that is not allowed
use either positive or negative edge...
 
Re: 16-bit shifting vhdl

Try this...

if(clk1'event and clk1 ='1') then
key_out_s(15 downto 4) <= key_out_s(11 downto 0);
key_out_s(3 downto 0) <= key_data;
if(row_indata="0111" and column_in="0111") then
key_data<="0001"; -- binary for 1
elsif(row_indata="0111" and column_in="1011") then
key_data<="0010"; -- binary for 2
....
....
end if;
end if;
 
Re: 16-bit shifting vhdl

omg thanks i got it!
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…