How to set up Quartus to simulate 2 VHDL files?

[Max++]

I have create 2 VHDL files in same project.
While I simmulate first file every thing is OK,
but when I simulate second file the software will always back to simulate first file.

How to setting when want to simulate second file(In Quartus ||).

 

[ikru26]

Re: Quartus || Problem

set the second file top level module as first when you compile the second time