Dec 11, 2006 #1 M Max++ Junior Member level 3 Joined May 24, 2006 Messages 29 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Thailand Activity points 1,495 I have create 2 VHDL files in same project. While I simmulate first file every thing is OK, but when I simulate second file the software will always back to simulate first file. How to setting when want to simulate second file(In Quartus ||).
I have create 2 VHDL files in same project. While I simmulate first file every thing is OK, but when I simulate second file the software will always back to simulate first file. How to setting when want to simulate second file(In Quartus ||).
Dec 11, 2006 #2 I ikru26 Banned Joined Feb 1, 2005 Messages 97 Helped 8 Reputation 16 Reaction score 7 Trophy points 1,288 Location INDIA Activity points 0 Re: Quartus || Problem set the second file top level module as first when you compile the second time
Re: Quartus || Problem set the second file top level module as first when you compile the second time