[SOLVED] how to set to high accurancy in analog design environment

[wdssll]

I'm doing layout with moscap. and i just copied the circuit to another one in the same schematic and did the post layout simulation. the results from the two identical circuits were different. and the reason is that the leakage current from the two moscap are different(2 times difference). so i want to improve the accuracy to see if it there is a program bug here. i have changed the tolerance to 10^-15 and cannot increase any more. the program told error. inability to compute dc points.
so could anyone tell me how to increase the accuracy further? thanks.

 

[dick_freebird]

If the leakage is -exactly- 2X different, check that you haven't
douple-copied an instance on top of itself (ought to warn) or
shorted two instances by copying their close-in named nets
and forgetting to rename.

Analysis>transient>options, you can look for cmin (ought to be
empty) and gmin (affects capacitance, none). There are also
the accuracy checkboxes on the transient form. But I am
suspecting something other than an accuracy-settings problem.

 

[wdssll]

thanks for your help.
it is not exactly 2X difference. i have checked there is only one copy and there is no same wire name for the two copies.
for schematic, the simulation results are identical. then i used moscaps' extracted view to do post layout simulation, other circuit components were using schematic, the leakage current are different. one is about 60fA, the other is about 140fA. I'm using chartered 0.18um process.
i think there must be something wrong. otherwise the computer would not be so smart to give two different answers.
Do you mean the model settings might be wrong? or the simulation setting? but the schematic simulation seems to be correct.

If the leakage is -exactly- 2X different, check that you haven't
douple-copied an instance on top of itself (ought to warn) or
shorted two instances by copying their close-in named nets
and forgetting to rename.

Analysis>transient>options, you can look for cmin (ought to be
empty) and gmin (affects capacitance, none). There are also
the accuracy checkboxes on the transient form. But I am
suspecting something other than an accuracy-settings problem.

 

[dick_freebird]

Look at the header of the spectre.out file. There should be a
report of all the tolerance settings.

Question why your capacitors leak at all. Is there a shunt R
in the subcircuit layer of the model hierarchy? Is the leakage
in the pcapacitor instead? If you examine the extracted view
for pcapacitors, and place pacapacitors in the schematic
view with the same properties and hookup, does the schematic
simulation take on the same character?

 

[wdssll]

it is p type moscap. the model is just a pmos transistor with drain and source connected together. there is gate leakage current, which causes the problem.
the pmos capacitor in schematic and in layout are of the same properties. DRC and LVS all passed.
I just wonder how come two same copies of mos capacitors' layout can generate different gate leakage current.

 

[dick_freebird]

Well, that is indeed the question. But schematic and layout
design-kit MOSFETs are likely no different between the views
(you could check the netlist files and see if any attributes are
different).

I still think it's either in additional components instantiated in
the netlist, or just node-bloat making a different netlist that
solves differently, within tolerances but less so.

 

[wdssll]

the netlist is ok. also following the cadence manual, i have almost increased to the max accuracy. it still does not work.

My supervisor said QRC rule may have problems. the leakage current should be very similar for schematic simulation and post-layout simulation. parasitic RC should not affect the leakage current by too much.

thanks very much for your help.

---------- Post added at 12:37 PM ---------- Previous post was at 12:35 PM ----------

Here is the instructions from cadence manual, in case someone may need it.

Suggestions for Improving Transient Analysis Accuracy

Verify that the circuit biased up properly. If it did not, there might be a problem in the
topology, the models, or the power supplies.

Be sure you are using appropriate models and that the model parameters are consistent
and correct. Check the operating point of each device.

Set the transient analysis parameter errpreset to conservative.

If there is a charge conservation problem, use only charge-conserving models if you are
not already doing so. Then tighten reltol to increase accuracy. (With the Spectre
simulator, only customer-installed models might not be charge conserving.)

Be sure that gmin is not influencing the solution. If possible, set gmin to 0 (in an
options or set statement).

If a solution exhibits point-to-point ringing, set the integration method in the transient
analysis to Gear’s second-order backward-difference formula (method=gear2only).

If a low-loss resonator exhibits too much loss, set the integration method in the transient
analysis to the trapezoidal rule (method=traponly).

If the initial conditions used by the Spectre simulator are not the same as the ones you
specified, decrease the rforce parameter in the options or set statements until the
initial conditions are correct.

If the Spectre simulator does not accurately follow the turn-on transient of an oscillator,
set the maxstep parameter of the transient analysis to one-tenth the size of the
expected period of oscillation or less.