How to set the environment for gate level simulation

[karalamoorthy_p]

Hi all,

I am new in gate level simulation.Please could you tell me how to set up the Gate level simulation.Is there any guide or notes to refer the gate level simulation. Please help me to further.


Thanks,
Karalamoorthy

 

[rca]

You need a netlist, a SDF, a std cell/macro models satin.

 

[vikas gupta]

What does it mean when we say that in GATE Level the whole design (may be netlist) is flattened? I had done GATE Level simulation in 2 steps...firstly Zero Delay..and then Standard delay format (SDF). What is the advantage of using Zero delay? Also how in terms of timing does it differ from RTL? I did find a timing problem when I ran the same test case for I2C from RTL to ZD (Zero delay). The problem was in generationg the stop condition. When I asked my senior this problem could not be caught in RTL..he told me that in RTL we actually force the signals while in zero dealy they actually travel the path ..(or something like this). I just mentioned the above problem you don't need to solve that...but what is not clear to me is what happens in zero delay in comparision to RTL in terms of signals travelling from one point in SoC to another.
Kindly reply.