Library ieee;
Use ieee.std_logic_1164.ALL;
ENTITY rise_fall IS
PORT ( clk, karma_1, karma_2 : IN STD_LOGIC;
R, F : OUT STD_LOGIC);--R is rising edge, F is falling edge
END rise_fall;
ARCHITECTURE rise_fall_arc OF rise_fall IS
SIGNAL rc, fc : STD_LOGIC;
BEGIN
process (karma_1, clk)
BEGIN
IF karma_1 = '1' THEN rc <= '0';
ELSIF clk'event AND clk = '1' THEN rc <= '1';
END IF;
END PROCESS;
------------------------2nd process
process (karma_2, clk)
BEGIN
IF karma_2 = '1' THEN fc <= '0';
ELSIF clk'event AND clk = '0' THEN fc <= '1';
END IF;
END PROCESS;
----------------------------3rd process
PROCESS (clk, fc, rc)
BEGIN
IF clk = '1' THEN
R <= rc;
F <= NOT rc;
ELSIF clk = '0' THEN
R <= NOT fc;
F <= fc;
END IF;
END PROCESS;
END rise_fall_arc;