Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to sense both falling and rising edges of a signal?

Status
Not open for further replies.

nlulani

Junior Member level 3
Joined
Nov 29, 2004
Messages
26
Helped
2
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
313
irq_falling

Hi all,
I wish to sense both the falling and rising edges of the a signal for two different purposes, but everytime i do so i get a bad synchronous error.
for example i write the little code below.

p1: process(Q,valid)
begin

if(valid='1') then
irq<= '0';
else
if(Q'event and Q='0' and mode = '0') then
irq <= '1';
elsif Q'event and Q = '1' and mode = '1' then
irq <= '1';
else
irq <= '0';
end if;
end if;
end process p1;

here the error comes like
ERROR:Xst:827 - c:/my_projects/advanced/i2/my_int_gen/int_gen.vhd line 80: Signal irq cannot be synthesized, bad synchronous description.
-->
can anyone of u tell me what can be done for it.
thanks and regards
 

nand_gates

Advanced Member level 3
Joined
Jul 19, 2004
Messages
893
Helped
175
Reputation
350
Reaction score
51
Trophy points
1,308
Activity points
6,843
Re: Help!!!

Hi
This code is surely not going to be synthesized!!!
Your problem is you dont think of hardware while
writing the VHDL or Verilog code! Think of hardware
first then use VHDL or Verilog to just describe Ur
hardwaware! That the reason they are known as
Hardware Description Language!!!
Hope this helps you write better VHDL or Verilog Codes!
 

nlulani

Junior Member level 3
Joined
Nov 29, 2004
Messages
26
Helped
2
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
313
Re: Help!!!

nand_gates said:
Hi
This code is surely not going to be synthesized!!!
Your problem is you dont think of hardware while
writing the VHDL or Verilog code! Think of hardware
first then use VHDL or Verilog to just describe Ur
hardwaware! That the reason they are known as
Hardware Description Language!!!
Hope this helps you write better VHDL or Verilog Codes!


Hi
thanks for reply,
but my question is still unanswered, just throw this code away and let me know if it is possible to sense both falling as well as rising edges of a signal if it is required for some application. i guess there may be tricks to do so...
the code was given just as an example.
thanks and regards
Nitin
 

Renjith

Full Member level 3
Joined
Jan 3, 2005
Messages
173
Helped
15
Reputation
30
Reaction score
6
Trophy points
1,298
Location
India
Activity points
1,710
Re: Help!!!

nlulani said:
let me know if it is possible to sense both falling as well as rising edges of a signal if it is required for some application.

Hi,
Ofcourse, u can do operations on both the edges of a signal.
But the way u wrote the code, is not at all a synchronous stmt.
Thatz y the synthesis tool cud n't process it.
 

nand_gates

Advanced Member level 3
Joined
Jul 19, 2004
Messages
893
Helped
175
Reputation
350
Reaction score
51
Trophy points
1,308
Activity points
6,843
Re: Help!!!

See if the following code works for you!!!

Code:
library ieee;
use ieee.std_logic_1164.all;

entity irq_logic is
  
  port (
    Q     : in  std_logic;
    mode  : in  std_logic;
    valid : in  std_logic;
    irq   : out std_logic);

end irq_logic;

architecture behavior of irq_logic is
signal irq_rising : std_logic;
signal irq_falling : std_logic;

begin  -- behavior
  with mode select
    irq <=    irq_rising  when '0',
              irq_falling when others;
  
rising_edege: process (Q, valid)
begin  -- process rising_edege
  if valid = '1' then                   -- asynchronous reset (active low)
    irq_rising <= '0';
  elsif Q'event and Q = '1' then        -- rising clock edge
    irq_rising <= '1';
  end if;
end process rising_edege;
  
fall_edge: process (Q, valid)
begin  -- process falling_edge
  if valid = '1' then                   -- asynchronous reset (active low)
    irq_falling <= '0';
  elsif Q'event and Q = '1' then        -- rising clock edge
    irq_falling <= '1';
  end if;
end process fall_edge;

end behavior;
 

sp

Full Member level 6
Joined
Jan 1, 2004
Messages
396
Helped
23
Reputation
46
Reaction score
2
Trophy points
1,298
Location
Floating Garden
Activity points
4,044
Re: Help!!!

Code:
Library ieee;
Use ieee.std_logic_1164.ALL;

ENTITY rise_fall IS
	PORT ( clk, karma_1, karma_2	: IN STD_LOGIC;
			R, F	: OUT STD_LOGIC);--R is rising edge, F is falling edge
END rise_fall;

ARCHITECTURE rise_fall_arc OF rise_fall IS
SIGNAL rc, fc	: STD_LOGIC;
BEGIN

process (karma_1, clk)
BEGIN
	IF karma_1 = '1' THEN rc <= '0';
	ELSIF clk'event AND clk = '1' THEN rc <= '1';
	END IF;
END PROCESS;
------------------------2nd process
process (karma_2, clk)
BEGIN
	IF karma_2 = '1' THEN fc <= '0';
	ELSIF clk'event AND clk = '0' THEN fc <= '1';
	END IF;
END PROCESS;
----------------------------3rd process
PROCESS (clk, fc, rc)
BEGIN
	IF clk = '1' THEN
		R <= rc;
		F <= NOT rc;
	ELSIF clk = '0' THEN
		R <= NOT fc;
		F <= fc;
	END IF;
END PROCESS;


END rise_fall_arc;

i try my best,,, and i use almost 5 hours to do it,, dunno it is correct or not...

whenever there is rising edge, the R will stay high and remain untill falling edge...
whenever there is falling edge, the F will stay high and remain untill rising edge...

hardware for 3rd process is using TRI buffer or multiplexer... i draw it then i write the code

this is the waveform simulation file...
 

Black Jack

Full Member level 4
Joined
Dec 2, 2003
Messages
236
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Location
UKRAINE
Activity points
1,817
Re: Help!!!

Generally, using BOTH rising and falling edges in design - bad idea.
You are mistakes if you think this can help maximize performance.
NOT exist design where neaded BOTH edges.

Clock like "tick" between EVENTS, so if you need both edges, your time base incorrect
 

sp

Full Member level 6
Joined
Jan 1, 2004
Messages
396
Helped
23
Reputation
46
Reaction score
2
Trophy points
1,298
Location
Floating Garden
Activity points
4,044
Re: Help!!!

Black Jack said:
Generally, using BOTH rising and falling edges in design - bad idea.
You are mistakes if you think this can help maximize performance.
NOT exist design where neaded BOTH edges.

Clock like "tick" between EVENTS, so if you need both edges, your time base incorrect

i thought it will increase the preformance... not?...

like our PC ram nowadays... we are using the DDR... double data rate... it is using the rising edge and falling edge to execute operation....

regards,
sp
 

nlulani

Junior Member level 3
Joined
Nov 29, 2004
Messages
26
Helped
2
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
313
Re: Help!!!

hi,
thanks for all the replies..
i have also sorted out a solution for the problem.
the problem was actually a single process cannt not detect both rsising as well as falling edge pf a signal. this is where i was mistaking, but now the thing is clear and i m also putting one solution for it.


irq <= (A and mode) or (B and not(mode));



process (IACK1, IACK4, IACK5, IACK2)
begin
VALID <= IACK5 or IACK4 or IACK2 or IACK1;
end process;

process(Q, valid)
begin
if valid = '1' then
A <= '0';
else
if Q'event and Q = '1' then
A <= '1';
else
A <= A;
end if;

end if;
end process;

process(Q, valid)
begin
if valid = '1' then
B <= '0';
else
if Q'event and Q = '0' then
B <= '1';
else
B <= B;
end if;

end if;
end process;



thanks and regards
Nitin
 

Black Jack

Full Member level 4
Joined
Dec 2, 2003
Messages
236
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Location
UKRAINE
Activity points
1,817
Re: Help!!!

sp said:
Black Jack said:
Generally, using BOTH rising and falling edges in design - bad idea.
You are mistakes if you think this can help maximize performance.
NOT exist design where neaded BOTH edges.

Clock like "tick" between EVENTS, so if you need both edges, your time base incorrect

i thought it will increase the preformance... not?...

like our PC ram nowadays... we are using the DDR... double data rate... it is using the rising edge and falling edge to execute operation....

regards,
sp

Try to estimate easy design like DFF -> (Logic) - DFF
with Timing Analyser for 1) both DFF with same edge 2) with different edge.
and you can see that in case 2) performance (Fmax) decreased by factor 2
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top