How to see CLK_IN signal in Virtex-5 at Oscilloscope??

[msdarvishi]

Hello everybody,

I am working on DCM operating at 450MHz in Virtex-5 FPGA with SPEED GRADE -1 in MAXIMUM SPEED. I used an internal clocking by setting the clock on LOC = AG18 in UCF. I would like to know how can I monitor this signal with oscilloscope. The board that I use is Xilinx Gensys Virtex-5 with XC5VLX50T device. Also, the PMOD connectors in this board are located in AD11, AD9,...

Thank you,

 

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I would like to know how can I monitor this signal with oscilloscope.

Seriously you have to ask how to do this?

Route the DCM's output internal clock to another pin and or use a DDR output register and connect the clock to the DDR output register and put a 1 and a 0 on the two DDR register data inputs.