Hi!!!
Could anyone tell me how to run synthesized simulation
(simulation tools is Cadence's nc-sim & compiler tools is Synopsys's DC)??
Which files to need??? *.sdf or *.v???
Could anyone to provide method for me ??
If you have any suggestion please let me more clear...
You actually do not need to the SDF file for gate level simulation, if you don't tend to do timing verification by running gate sim. Turn off the dealy by adding "zero_delay_mode", (I can't remember very clearly, check the NCSIM manual). Or, simply slow down the clock.
just after synthesis, you can run simulation on netlist + library verilog modek with
zero delay mode.
of course, you can also write a sdf file in DC, and run simulation with the sdf file.
after APR, you can get accurate sdf file, it means you can run post-simulaiton.