how to roundoff to 8 bits in verilog

[vny]

hello,
am doing my project in iverilog . i have reached a particular stage where i get a 17 bit out put from a 8 bit input(after multiplying and sign adjustments stages). now i want to revert back my 17 bit input to the first stage input register which is actually 8 bit. how can i round off 17 bit to 8 bits . there are some negative numbers also which is represented in 2's complement form.

please help as i am stuck with this and not able to proceed further

 

[guitarguy12387]

There's a number of rounding algorithms out there (google will help).

The easiest is just to add new_lsb-1 before truncating. Simple and effective, but it will have a bias.

 

[imbichie]

Hi,

There are many ways to approach this type of problem..You can try these things...

one way is that You can use the both input and output bits as 17, by appending zeros to the input so both the input and output bits are same in number.

Another way is that your inputs are 8 bits, so you can selects the bits which are used to be the next 8 bit input out of these 17 bits output, so you can selects the msb 8 bits, or lsb 8 bits or any 8 bits from the 17 bits output ...

 

[vny]

sorry for the delay and thanks alot for the replies . i actually made all the bits as 17 bits and did the calculations as i need minimum 16 bits to represent my final result .initially i checked the 13th bit and then adjusted the remianig bit as we used to do it in manual way . but in the long run it wont support because of the numbers i give for multiplication. the precision could not be conained in 13 bits. hence i changed it to 17.

thanks alot for the help
vini