how to resolve LEC not-mapped point in power IO ?

[Korver]

Dear all :

1. when I compare pre-APR(golden netlist) and post-APR(revised netlist) , Power IO "VSS" is not-mapped point for Z in golden netlist . But VSS in post-APR is defile by supply0 , not input signal . So LEC can't mapped point to VSS. How can I let it mapped? Thanks you.

pre-APR : Input VSS;
post-APR: supply0 VSS;

2. same as question 1. .When power VDD in post-APR defined supply1 , so sub-module not connect to VDD in post-APR netlist. How can I let it mapped? Thanks you.
post-APR:
module chip_core
supply1 VDD;
chip_core_sub_0 sub1 (
.AVDD()
);

pre-APR:
module chip_core
input VDD;
chip_core_sub_0 sub1(
,AVDD(VDD)
);

 

[sp]

modified the netlist to either use input declaration or use supply* for both side.
then sign-off by another person, it should be safe enough.