How to relate modules in Verilog ?

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test_out

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Verilog question!

Hi, im new in circuit designing. Now my project have some modules, and these module have relationship. So how can I relate them together?

Thanks
 

Verilog question!

please connect them together using wire!!
 

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    test_out

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Re: Verilog question!

you should write a top file to combine sub-module files.

Regards
/David
 

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    test_out

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Re: Verilog question!

hi,
find a verilog book and have a look, it's fundamental skill in design
 

Re: Verilog question!

Hi

Call all your submodules in your top module
 

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    test_out

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