how to reduce the size of a design during synthesis

[rashmidesai]

hi all,
I am into static timing analysis department and i am new to this field. i have to reduce the size of the design.. the instance count in my design is some roughly 50000 n say suppose i have to reduce it to around 30k or so whats the procedure to do it

 

[rca]

First you need to synthesize without any timing constraint, to see what is the smallest area you could have with your design. After by adding constraints you will add more buffer to fix timing.
If you did not reach the area, you need to change your rtl.

 

[rashmidesai]

by commenting some inputs and outputs reduce the cell count in the module?

 

[kel8157]

by commenting some inputs and outputs reduce the cell count in the module?

Yes indeed. Synthesis is similar to trying to lose a few kilos of weight. :lol:
The easiest is as you said, cut off an arm and a leg from the fat person, it can reduce 50Kg to 30Kg in minutes.. :twisted:
Next logical way is to ask your boss to give you a training in synthesis. ;-)
Third is tough and may not work. Use compile with map effort high, and optimize for area. But I doubt that would cut 20Kg out of 50.. :|