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how to recognize `defined on tb_top.v to tb_sub.v on verdi compiler?

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billylee

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hello everyone :)
I have question on verdi compiler.

Usually we use parameters with pre-processor keyword `define

I defined on tb_top.v like this,

`define TARGET_FPGA
`ifdef TARGET_FPGA
`define SBIT 8
`else
`define SBIT 6

and I used parameter on tb_sub.v that defined on tb_top like this,

module tb_sub (
input [`SBIT:0] A,
input [`SBIT:0] B,
output [`SBIT:0] O
);

In this case, vcs or ncsim compiler dose not make trouble to interpret the pre-processor

BUT, verdi compiler make a noise.
*Error* failed to find identifier SBIT

how can I avoid this message??

Best Regards,
Billy
 

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