how to really reduce charge_injection in switch ??

[GDF]

1)So, no way can cancel the charge injection well up to now? is this a good
research topic?
2)Besides, we also see the charge injeciton effect in simulation, both in time
domain analysis and THD result. But the result is suspect?
3)How do I know how much charge injection is improved by simulation?
Or, the only thing I can do is just try all the methods and ignore the simulation?

 

[ocarnu]

1) there are more methods to either reduce it or transform it in a constant voltage (see clock boosted switches). Is not a good research topic becuase everything was done.
2,3) in simulation you cancel the charge injection completely, but this won't happen in a real circuit. You should extract with parasitics, run corners and you will get an idea.

 

[SkyHigh]

I think I was late to help.

One common method used by analog IC designers is to use advanced clocking at the shunt MOS. For details, refer to Ken Martin - Analog IC Design.

Another method is to transmission gates instead of NMOS. For details refer to Ken Martin - Analog IC Design.

Razavi's book is too theoretical and not deep enough. Perhaps in the US Razavi's book is commonly used. But Ken Martin's and Gray & Meyer, sometimes Allen's book, are much deeper and challenging for practising analog IC designers, for Asia and Europe. In Europe, Razavi's book doesn't sell well because it is not deep enough.

 

[ocarnu]

Come on, I read a lot of books on analog desing and Razavi's is one of the best. It does not cover everything, that is a undergrad book. Actually, Gray's better, but too detailed. Useless detail. Martin, for some reason I just don't like. Still, it is very usefull. But go ONLY with Martin to an interview and you will fail in no time.
Anyway, last time I checked on the "great" asian (even european) analog designers, they were working in Austin or San Jose. Tell me how many companies outside US use these amazing profound designers.

 

[tuza2000]

how about the coms switch?

dummy transistor is a good choise,but sometimes the cmos switch is used more popular

 

[Freakwency]

how about the coms switch?

dummy transistor is a good choise,but sometimes the cmos switch is used more popular

The complementary switch may help, but the matching between the PMOS and NMOS is still another issue.

 

[GDF]

Anybody has the idea how to check the effect of charge injection in simulation?

 

[mists]

i heared that the current spice model is not very accurate for charge injection simulation, but i am not sure.

 

[rfsystem]

This is my second reply:

I share the view that Razavi books provide less detail. He start presenting analog IC design with less math detail. That help to interest more people diving into analog. Earlier or later they have to get into detail of analog, which means math, otherwise they could not make dimension analysis or fail to predict and trade second order effects. That is needed in job. Hacking schematics and looking for waves is very ineffective. And you will block yourself getting more insight. So please do not stick with Razavi.

For SC circuits the charge-injection is an offset if it is not signal dependend. That offset could cancel up to mismatch if balanced circuit are used. The signal depend charge injection introduce nonlinear distortion. The second order component cancel up to mismatch by balanced circuits.

The injection could be reduced by dummy elements. The exact charge transfer is reasonable modelled in BSIM3V3 and up. If the model does not have S/D balanced model parameter setup for gate/drain and gate/source caps you can use two devices in schematic antiparallel. Extraction with an unbalanced model is not possible.

At the time of the switching the impedance of the source and the drain side have an effect on the charge distribution. But if SC circuits are used it does not matter where the charge is flowing after the channel is conducting. So more critical is the charge before conduction takes place. So you could analyses the charge effect before making connection and after. A constant, voltage independend gate/source or gate/drain cap works for the first analysis. Depending on control voltage and the potentials on both sides before conduction the 3 charges could be expressed.

So you could imagine that math is the base for an indeep analysis of a such a silly thing like charge injection.

If you try to avoid math you will fail.

 

[GDF]

I got a simulation result as attachment.
I fed a 2KHz sine wave to the SC low pass filter, whose 3dB frequency is 20KHz,
and the sampling rate is 900KHz. I got a wave form of the output of SCF, and use
dft function of the calculator in cadence. I got a result as attachment. We can
see the 3rd and 5th order harmonics in the plot. But, besides those harmonics of
fundamental, we also got the spurs at 30KHz, 34KHz, 62KHz and 66KHz...etc.
The voltage magnitude of fundamental frequency 2KHz is 620mV the 3rd and
5th are 0.26mV and 0.18mV.
1) Do I need to add other frequency components in addition to 3rd and 5th?
or just calculate 3rd and 5th? so the THD is around 66dB?
2) Anybody can explain why I got this result?

Thanks,

 

[phoenixsmk]

use smaller size switches and fully differential