how to really reduce charge_injection in switch ??

[andy2000a]

/kabuki.eecs.berkeley.edu/Ëœtcho/thesis1.pdf

Hi
Razavi book said , use dummy MOS can reduce charge_injection
and clock feed thru , but in hspice simulation , and real chip ASIC
sample/hold circuit , I can not find dummy MOS have wrok

why ??

 

[mists]

maybe different input is a good choice

 

[andy2000a]

from Razavi Book said use differential is Good design .. I know it ,

but I problem is , if I use one path design , and text book said reduce by
dummy mos , hspice can not find it , the truth is "textbook"
or "hspice" , I think hspice maybe accuracy ..

have anyone know another method to reduce ( single path )

 

[Humungus]

A way to reduce charge injection is to put another switch that connects, assuming your input is on the top plate of the capacitor, the bottom plate of the capacitor to ground.

Once you have sampled your signal, first open the bottom plate switch. This would always produce the same ammount of charge injection. Then, when the main switch is opened, no extra charge injection will appear.
By doing so, charge injection only accounts as a fixed offset, which can be removed.

This method removes signal dependent charge injection, which in most cases is the most anoying component.

 

[rfsystem]

The charge injection is two effects.

1. CGDO or CGSO overlap cap.
That is a signal independed injection because the cap is linear. It could be compansated by a complementary driven MOS with half of the width and source and drain connected together to the cancelation node. The orientation should be equal.

2. Impedance dependence charge distribution.
The CGS and CGD channel cap injection has in most case equal charge distribution between sourse and drain. If the impedance is different the charge injection is also not 50%. So the balance does not work perfect. But I have seen rare circuits optimizing this effect.

 

[Hughes]

Use cmos trans gate may have a better result. But charge injection can not be cancelled completely.

 

[linxf2003]

I have seen some designs using a shorted mos transistor with same type as the switch transistor to better match the charge.

 

[Hughes]

I have seen some designs using a shorted mos transistor with same type as the switch transistor to better match the charge.

I guess this method is what andy2000a proposed in the question -- dummy MOS.

 

[electronrancher]

looks like it.

rather than dummy mos, differential input is the only way i've seen to actually cancel out that burst of charge on a switching cycle. each input gets chopped by the same size transistor, so the chopper injection becomes common mode and is damped quite a bit by the PSRR of the amp

 

[hebu]

But, I think the differential structure can improve the charge injection but
not exact. The signal depedent charge is depedent on the signal
level, definitely, the differential signals have different signal levels.
So, the charge injection level is also different.

 

[eda4you]

Reduce the rise and fall time of the clock!!!!

 

[Mline7]

Humungus and rfsystem have given you the right explanation concerning the ways to get rid of charge injection.

Concerning the differences between your hspice simulation and the theory, it simply comes from the fact that your transistor model simply don't account for chanel charge injection (the clock feedthrough, which is the coupling between switch gate and source through Cgs is sometimes included in charge injection, however it is easily modeled by the Cgs capacitor).

In fact, the chanel charge injection is very difficult to model. It depends on the input signal, on the gate slope, on the impedance seen from the source and from the drain. So, to simplify this, the usual transistor models simply feature a parameter (XPART for BSIM3v3) which value can be set to (as far as I remember):
- 0: 0% of chanel charge is transmitted to the source, and 100% to the drain
- 0.5: 50% of chanel charge is transmitted to the source, and 50% to the drain
- 1: 40% of chanel charge is transmitted to the source, and 60% to the drain

So, you've got to konw how your charge injection will be shared between source and drain (cf. rfsystem and Humungus), and then set the corresponding XPART value in you MOS model to correctly simulate your circuit.

 

[eda4you]

Hallo Mline71

The ratio (quote) of charge flowing to source or drain depends strongly on the rise and fall time. Simulation models are very worse. So you definitely cannopt trust the simulator. BTW if the rise/fall time is slow, the mos keeps longer during the switch off process in linear and than in saturation mode -> which results that most of the channel charge flows to the source and only less to the drain.

 

[Btrend]

BTW if the rise/fall time is slow, the mos keeps longer during the switch off process in linear and than in saturation mode -> which results that most of the channel charge flows to the source and only less to the drain.

As I know from text books, charge injection has two kind (maybe more ?):
1. Clock feedthrough : which is from CGSO, CGDO. and it occur only when the switch rising or falling. cause CGSO/CGDO form a high pass path from gate to S/D. and the noise is (VH-VL)*CGSO/(CGSO+Cs), where CS is the sampling cap.
during the clock high state, there is no more clock feedthrough noise.
and slow rise/fall time pulse (lower frequency) will be attenuated by the high pass filter (CGSO/CGDO). so noise will be smaller
2. Channel charge injection: which is from the channel charge formed previously when the swith is in ON state, u can imaing there is channel capacitor between source and drain. When the switch is OFF, these channel charge can not be absorbed to the substrate (chage conservation), so it will find a way (a low impedance path) to escape from the channel. the best way is the sampling cap.
so u will get a noise at Cs. but the rise/fall time has nothing to do with this channel charge, it depend on only ON or OFF state of the switch.

if I am wrong, correct me. thanks

 

[eda4you]

There is NO suddenly way to switch the transitor for on to off. Imagine the case the gate voltage decrease with the fall time. In case Vgate - Vth < Vd the Mos is in saturation. The channel is pinched-off. So more channel charge flows into the source as into the drain. A simple on-off modell don't explain how channel charge injection escapes.

 

[Btrend]

at the end of sampling , the VDS should be equal approximate to 0, such that u get the right input voltage(VS=VD). So, the SWITCH should be in triode region. After the end of ON, the Vgs decrease from VDD to 0, but the VDS is still low if the input signal (VD) do not cahnge abrupt.

 

[hebu]

So, the conclusion is that it's diffcult to see the effect of charge injection in
simulation? but what's the glitch we can see in SC filter simulation?
who cause this phenomenon? And, how to know the performance of the means
used to overcome the charge injection?

 

[Btrend]

refer to the appendix1 in the following pdf
**broken link removed**

 

[hebu]

I have one question on the dummy switch with inverse clock to solve charge
injection. Since the turned-on dummy can suck the charge of turned-off switch,
is it possible for the switch itself to suck the charge it left last phase?

 

[ocarnu]

No, becuase it sucks the charge from the lower impendance branch, i.e. the signal source. Anyway it doesn' matter, you hold phase was corrupted. The track phase is fine anyway.