nnmate
Junior Member level 1
Hi all,
Does anyone here know, how to realize a Finite States Machine by Verilog-A for Cadence IC Tools? I have already got .vhdl file with lines like
" variable next_state: states;
variable current_state: states;".
Donno how to do it with verilog-a to generate a behavioral model.
PS1: this is a digital control block. States are followed one by one locked by vclock.
PS2: the FSM is not a must, I just don't know how to control the timing without FSM, exp. next_state=state5
thanks alot
Does anyone here know, how to realize a Finite States Machine by Verilog-A for Cadence IC Tools? I have already got .vhdl file with lines like
" variable next_state: states;
variable current_state: states;".
Donno how to do it with verilog-a to generate a behavioral model.
PS1: this is a digital control block. States are followed one by one locked by vclock.
PS2: the FSM is not a must, I just don't know how to control the timing without FSM, exp. next_state=state5
thanks alot