wr_ena_data <= '1' when i_spi_rxst = "000" else '0';
spi_rxd_rst_in(7 downto 0) <= i_spi_rxd;
spi_rxd_rst_in(10 downto 8) <= i_spi_rxst;
cntr_write : entity work.upcntr generic map (12) -- counter for the number of data written in the fifo of each message
PORT MAP (
c => i_wr_clk,
ar => i_rst,
sr => wr_en_latch,
ce => wr_ena_data,
q => cnt_bytes_wr);
cntr_latched : entity work.dreg_clr_sclear generic map(12) -- save the counter value
port map(
c => i_rd_clk, --i_clk,
ar => i_rst,
sc => '0',
e => rd_ena_latched,
d => cnt_bytes_wr,
q => val_cnt_written);
wr_clk_not <= not i_wr_clk;
wr_ena_fed : entity work.fed -- falling edge detector to reset the counter of written data
port map(
c => wr_clk_not, -- Clock
ar => i_rst, -- Async active high Reset
d => wr_ena_data, -- D data in
feu => open, -- Falling Edge tick, Unregistered
fec => wr_en_latch -- Falling Edge tick, Registered
);
rd_clk_not <= not i_rd_clk;
rd_ena_fed : entity work.fed -- falling edge detector to start the read data counter.
port map(
c => i_rd_clk, -- Clock
ar => i_rst, -- Async active high Reset
d => wr_ena_data, -- D data in
feu => open, -- Falling Edge tick, Unregistered
fec => rd_ena_latched -- Falling Edge tick, Registered
);
rd_ena_start : entity work.dreg_clr_sclear generic map(1) -- stays at 1 as long as the counter is less than or equal to the value of written data
port map(
c => i_rd_clk, --i_clk,
ar => i_rst,
sc => clr_rd_latch,
e => rd_ena_latched,
d(0) => '1',
q(0) => rd_en_latch);
cnt_read : entity work.upcntr generic map(12) -- data counter read in each message.
port map(
c => i_rd_clk,
ar => i_rst,
sr => clr_rd_latch,
ce => cnt_rd_latched_en,
q => cnt_bytes_rd);
cnt_rd_latched_en <= cnt_rd_latched and rd_en_latch;
cnt_rd_latched <= '1' when cnt_bytes_rd <= val_cnt_written else '0';
clr_rd_latch <= '1' when cnt_bytes_rd > val_cnt_written else '0';
U_spi_data : l1_coregen_spi_data -- -- FIFO Memory
port map(
rst => i_rst,
wr_clk => i_wr_clk,
rd_clk => i_rd_clk,
din => spi_rxd_rst_in,
wr_en => wr_ena_data,
rd_en => cnt_rd_latched_en,
dout => spi_rxd_rst_out,
full => open,
empty => spi_empty,
valid => open,
rd_data_count => open,
wr_data_count => open
);