How to read output ports of the DUT using SytemC and ncsim?

[silicon_selva]

Hi,
I am using Cadence ncsim, DUT and Testbench are in VHDL.
1. How do I read some output ports of the DUT using SytemC?
2. How do I read the output ports of the DUT using ncsim?

Thanks & Regards.
selva