How to read output ports of the DUT using SytemC and ncsim?

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silicon_selva

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Hi,
I am using Cadence ncsim, DUT and Testbench are in VHDL.
1. How do I read some output ports of the DUT using SytemC?
2. How do I read the output ports of the DUT using ncsim?

Thanks & Regards.
selva
 

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