Oct 21, 2007 #1 A anantha_09 Member level 4 Joined Jan 28, 2007 Messages 75 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,771 Can you produce this sequence? Draw the schematic, hint: use a shift register. 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1
Can you produce this sequence? Draw the schematic, hint: use a shift register. 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1
Oct 21, 2007 #2 Old Nick Advanced Member level 1 Joined Sep 14, 2007 Messages 479 Helped 68 Reputation 136 Reaction score 18 Trophy points 1,298 Activity points 4,243 Re: interview question shift right, invert the bit that falls off the right and feed it into the left end of the shift register.
Re: interview question shift right, invert the bit that falls off the right and feed it into the left end of the shift register.
Oct 21, 2007 #3 A anantha_09 Member level 4 Joined Jan 28, 2007 Messages 75 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,771 Re: interview question hav u got any more problems of this kind or let me know wher can i find some of these kind
Re: interview question hav u got any more problems of this kind or let me know wher can i find some of these kind
Oct 23, 2007 #4 C cherjier Member level 5 Joined Dec 6, 2006 Messages 84 Helped 6 Reputation 12 Reaction score 1 Trophy points 1,288 Activity points 1,909 Re: interview question anantha_09 said: Can you produce this sequence? Draw the schematic, hint: use a shift register. 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Click to expand... hum.....not sure which is the best answer but my answer would be. RTL: reg shift [3:0]; always @(posedge clk or reset_n) begin if (!reset_n) shift <= 4'b0000; else shift <= {!shift[0], shift[3], shift[2], shift[1]} end correct? if wrong pls let me know
Re: interview question anantha_09 said: Can you produce this sequence? Draw the schematic, hint: use a shift register. 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Click to expand... hum.....not sure which is the best answer but my answer would be. RTL: reg shift [3:0]; always @(posedge clk or reset_n) begin if (!reset_n) shift <= 4'b0000; else shift <= {!shift[0], shift[3], shift[2], shift[1]} end correct? if wrong pls let me know
Oct 23, 2007 #5 V vamsi_addagada Full Member level 2 Joined Jul 5, 2007 Messages 132 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location bangalore Activity points 2,071 interview question hi anantha u are given that sequence is the detected johanson counter.it is working the last ff output inverte to the feed back of the first ff input.u want more details u r study the johanson counter vamsi
interview question hi anantha u are given that sequence is the detected johanson counter.it is working the last ff output inverte to the feed back of the first ff input.u want more details u r study the johanson counter vamsi