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fix setup time:
Wll this is not simple, but has you just have asked for bullet points, I would
1. Make sure you have right constraints(v.imp)
2. Make sure you have correctly identified flase paths and multicycle paths
3. Cell re-sizing may fix a few of those
4. Make larger floorplans to aviod extra congestion in PnR
5. Look for pipeliing opportunities in your RTL of the block which gives setup prob
6. Try to move logic around flops in your RTL
7. Some time a single register may be overloaded, you can have paralle registers to reduce loading, and hecne improving the critical path delay
8. Extract parallelism in your block architecture, and then do the RTL.
9. RTL coding style can hugely affect the critical path, make sure you use an experienced designer for this task.
fix hold time:
1. Enlarge the area while floorplanning, of the block which has hold violations, so that the pnr tools can put hold buffers in
2. Make sure your constraints are ok.