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How to perform post-synthesis sim with synplify results?

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snakebites

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The output of synplify is .vm. How to perform simulation with .vm files?
I just change .vm into .v,and perform sim in modelsim.Neither using testbench nor macro files(.do) can I give stimulus to input ports,such as clk, so the results are either 0 or x. BTW, modelsim didn't generate any error message during simulation.
What shou I do?
 

snakebites said:
The output of synplify is .vm. How to perform simulation with .vm files?
I just change .vm into .v,and perform sim in modelsim.Neither using testbench nor macro files(.do) can I give stimulus to input ports,such as clk, so the results are either 0 or x. BTW, modelsim didn't generate any error message during simulation.
What shou I do?
Click to expand...

I think you need to double check you testbench and macro files.
The .vm is really the verilog netlist file.
 

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