I'm drawing the layout for a rf power amplifier and I would like to know if there are other ways of optimizing the transistor (other than finger) to reduce the parasitics of the transistor?
What are the techniques used normally for drawing transistor layout in rf power amplifier?
Take advantage of the finger structure by interleaving forward and return current pathes. Some 100pH will impact at least your simulation result if not the performance or stability. Make a subcircuit modelling of the PA layout. IC RCX extractors are useless because the inductive coupling is not extracted. If 10mV is the error tolerance of the extraction and 200mA at 5GHz are flowing trough your layout the extraction should be accurate to 1.6pH(1.6e-12H)!!!. The extration tools today are focused on digital. So there is no market. But FastCap and FastHenry are useful or doing planar EM simulation.