How to NOT use while() loops in verilog (for synthesis)?

[user_asic]

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as:

while (num < test_number)
     begin
     .
     .
     .
     num = num+1;
     end

This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches. What would be the equivalent synthesizable of code of the above code segment?

Thank you

 

[RBB]

for loops are synthesizable.

reg [3:0] num;
reg [4:0] test_number = 4'hF;

initial
  for(num = 0; num < test_number; num = num + 1)
    begin
      ///////
    end

 

[user_asic]

I dont see how the for() loop is any different. test_number is entered at run-time.

 

[RBB]

I'm not sure what you're asking then.

 

[user_asic]

The loop will not be in a always or initial block.

I need a synthesizable equivalent of while() loop I posted.

 

[RBB]

Well the while module will have to be inside an always block in synthesizable or non-synthesizable code. Same with the for loop.

 

[amraldo]

This is how I see it.

You will have to increment num under clock control and if the num value is less than num_test then execute the code.

An always block will be enough. You have to take define num and num_test such that they can hold the largest value you can pass at run time.

--
Amr Ali

 

[kalyansumankv]

Hey user_asic

u can try if condition for sysnthasizable RTL as shwn

always @ (posedge clk)
if(num < test_number)
begin
.
.
.
num <=num + 1;
end

 

[user_asic]

yea kalyansumankv, thats how I managed to solve it.