how to model the testbench for bidirection_bus?

[kimjin]

vsim-3053

in my design ,i used a bidirection_bus,it's the type of inout,inout [3:0] data_bus;
in my testbench, i identified the signal:reg [3:0] data_bus;
but in the modelsim, it reports a error when i load the simulation program bidir_bus_test.v,the error said:
Error: (vsim-3053) E:/vhd/bidir_bus/bidir_bus_test.v(14): Illegal output or inout port connection (port 'data_bus').
# Region: /bidir_bus_test/u1
i'd wonder how to simulation the bidirection_bus,who can help me?
thank you.

 

[nand_gates]

(vsim-3053)

here is how you need to handle bi directional ports!

inout [3:0] data_bus;
// use following register to drive the data..
// if you are not driving any data on bidirectional data bus
// asssign Z to data_bus_reg
// for reading data from bidirectional bus use "data_bus" directly!

reg [3:0] data_bus_reg;

assign data_bus = data_bus_reg;

Hope this helps!

 

[kimjin]

bidirectional bus testbench

it does work.
thank you very much.

 

[jnanabindu]

illegal output or inout port connection (port

try out this link.

**broken link removed**