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How to model #delays in RTL?

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vlsi_fanatic

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#delays in RTL

hi,
can anyone tell me how to model delays in RTl?

thanks
 

always@smart

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Re: #delays in RTL

hi vlsi_fanatic,

i'm not sure what actually u ask.

In verilog i model the RTL delay in this way:



---------------------------------------------
always @(posedge clock)
b <= #1 a; //for synchronous design


assign c = b; //for asynchronous design

------------------------------------------

you will see b=a and c=b at 1ns delay after posedge clock . this code is still synthesizable, the #1 will be ignored by the synthesis tools, since it's not the actual delay phsically.


hope i answer ur doubt.

regards,
smart
 

vlsi_fanatic

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Re: #delays in RTL

#delay will be ignored by the synthesis tool as u said. but if i want some delay then how can i do it?
 

always@smart

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Re: #delays in RTL

vlsi_fanatic said:
#delay will be ignored by the synthesis tool as u said. but if i want some delay then how can i do it?


---------------------------------------------------------------------------------------

u meant u wanna add some delay at gate-level? i think it can be done using synthesis tools, by adding some buffer on the net.

another way is use analog delay circuit.

regards,
smart
 

BrownBear

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Re: #delays in RTL

#delays are necessary in RTL when in projects are behavioral models of non-digital circuits, for instance memory. In memory behavioral models are setup, hold, recovery and other timing checks. The only way to provide this timing requirements is use #delay.
Another advantage of having #delays is verifying design by waveforms become more easy .
 

marksile

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Re: #delays in RTL

This is no delay in RTL. you can add somes buffer in circuit if you wish some delay during synthesis.
 

AlexWan

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#delays in RTL

Hi, marksile

Only synthesisable RTL coding don't prompt delay.

Why to add buffer during synthesis???
 

vlsi_fanatic

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Re: #delays in RTL

Hi thanks for the replies but consider this situation. I am modelling a traffic signal. The R-R delay and G-Y delay may not be equal. So how can we model this? i mean if both the lights are red they can be so only for suppose x time units. and G to Y takes y time units. How to model this?
 

viswa

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Re: #delays in RTL

hi vlsi fanatic,
to achieve exact delays, run a counter and after u acheive ur required no of clock cycles,make approximate changes.its simple but i dont know whether i answered ur question.
 

JesseKing

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#delays in RTL

You should use non-block delay form in non-block evaluation, as
y <= #delay a + b;
and use block delay form in block evaluation or assign, as
#delay y = a + b;
if not, you might meet with some problem in some simulators.
 

hover

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#delays in RTL

The correct way to achieve a exact delay is using counter. In your example you can use one couter, when the value reaches x it cause a event(R to R), when reaches y it cause another event(G to Y).
 

soccer

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#delays in RTL

rtl delay is not support by synthesis tool, but you can define the timing delay in your timing constrain files for synthesis and layout flow.
 

bendrift

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Re: #delays in RTL

JesseKing said:
You should use non-block delay form in non-block evaluation, as
y <= #delay a + b;
and use block delay form in block evaluation or assign, as
#delay y = a + b;
if not, you might meet with some problem in some simulators.
u can use delay like above in RTL.but these are only for simulation before synthesis. during synthesis , design compiler will ignore them.so ,if u want to add delay in circuits ,u should add shift register or count in your RTL for real delay.
 

jitendra

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Re: #delays in RTL

Hi vlsi_fanatic,
Delays are ignored in synthesis.
In your case where you want to control some events, you can use counters.
You can use state machine such that particular light will be on/off in some particular state, and state transition can be done using counters.
For example state machine will remain in state "Green_state" for 100 clks and output "Green_out" will be asserted in this state and so on.

Regards,
Jitendra
 

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