vlsi_fanatic
Junior Member level 1
#delays in RTL
hi,
can anyone tell me how to model delays in RTl?
thanks
hi,
can anyone tell me how to model delays in RTl?
thanks
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vlsi_fanatic said:#delay will be ignored by the synthesis tool as u said. but if i want some delay then how can i do it?
u can use delay like above in RTL.but these are only for simulation before synthesis. during synthesis , design compiler will ignore them.so ,if u want to add delay in circuits ,u should add shift register or count in your RTL for real delay.JesseKing said:You should use non-block delay form in non-block evaluation, as
y <= #delay a + b;
and use block delay form in block evaluation or assign, as
#delay y = a + b;
if not, you might meet with some problem in some simulators.