How to model 2 concurrent processes in verilog

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I am trying to code a system in behavioral verilog that has 2 processes running concurrently. One is a serial input buffer that continuously monitors the input line for valid data (let's call this process A). The other is a process that kicks off when valid data is detected and passed to it. It then crunches the newly detected input and spits out the output. While this is happening, process A continues monitoring the input line for valid data. Any suggestions on how to model this behavior and its handshaking signals in verilog? Thanks in advance.
-Fabian
 

My answer can be you can write two concurrent process A and B.

I have few questions:
1. When do you can valid data for Process A.
2. When does process B should start processing data.
 

This is real easy to do using a mailbox if you can use SystemVerilog. (supported by any version of Modelsim). Process A does a mbox.put(valid_data) when it gets valid data. Process B does a mbox.get(data) and is blocked until the other process does a put.

If you can only use Verilog, then we need to know how time is consumed by each process. How long can B take to crunch on the input before sending an output. Can valid input come faster than it takes to crunch it (i.e. do you need many concurrent B processes?
 


Thanks for the reply.
Process B(processing) is assumed to be much faster than A(receive data). Reason being that process B runs on a data clk which is much slower than the system clk that A runs on.

- - - Updated - - -

A valid data word is indicated by another signal, transmit_start.
B should start processing whenever a word is completely received.
 

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