jackkb
Newbie level 1
Dear all,
I have an issue of using I2C MasterCore from OpenCores when I need to map to FPGA. The issue related to handle bi-directional SCL and SDA ports.
I download the code from https://opencores.org/project,i2c. I create a top I2C (I just care about SCL and SDA inout port, for other port, I temporarily ignore it)
I do not understand the following.
- If we use simulation, we need to pullup SCL and SDA by pullup(SCL) and pullup(SDA) in testbench to make sure that when scl_padoen_o = H, SCL is 1'bz, and the pullup(SCL) will make SCL = H in this case. For SDA, I also think it is same as SCL.
But pullup() is not synthesizable! In this case, if I need to map to FPGA, how can I "pullup" SCL or SDA?
I already read the post https://www.edaboard.com/threads/159731/, but I can not find the answer for my question.
If you have any idea for this, please give me.
Thank you so much.
I have an issue of using I2C MasterCore from OpenCores when I need to map to FPGA. The issue related to handle bi-directional SCL and SDA ports.
I download the code from https://opencores.org/project,i2c. I create a top I2C (I just care about SCL and SDA inout port, for other port, I temporarily ignore it)
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module iic_config( inout logic SDA, inout logic SCL, // Other input, output port); wire scl_pad_i; wire scl_pad_o; wire scl_padoen_o; wire sda_pad_i; wire sda_pad_o; wire sda_padoen_o; /* setup tri-state buffers for SDA and SCL */ assign SCL = scl_padoen_o ? 1'bz : scl_pad_o; assign SDA = sda_padoen_o ? 1'bz : sda_pad_o; assign scl_pad_i = SCL; assign sda_pad_i = SDA; i2c_master_top i2c_core( .scl_pad_i (scl_pad_i), .scl_pad_o (scl_pad_o), .scl_padoen_o (scl_padoen_o), .sda_pad_i (sda_pad_i), .sda_pad_o (sda_pad_o), .sda_padoen_o (sda_padoen_o), .*); endmodule
I do not understand the following.
- If we use simulation, we need to pullup SCL and SDA by pullup(SCL) and pullup(SDA) in testbench to make sure that when scl_padoen_o = H, SCL is 1'bz, and the pullup(SCL) will make SCL = H in this case. For SDA, I also think it is same as SCL.
But pullup() is not synthesizable! In this case, if I need to map to FPGA, how can I "pullup" SCL or SDA?
I already read the post https://www.edaboard.com/threads/159731/, but I can not find the answer for my question.
If you have any idea for this, please give me.
Thank you so much.
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