shm
Newbie level 4
Dear all,
Hello,
I have a problem with USB1.1 Quartus project from Open-Cores (usbhostslave). I can not figure out how to connect and mange the input/output ports in its project and in which way I can map them to physical USB connector's pins.
Precisely, I need a project that works with this IP Core and has been implemented on one of Altera/Xilinx's FPGA boards.
Is there any one that could help me?
Thanks in advance,
SHM
Hello,
I have a problem with USB1.1 Quartus project from Open-Cores (usbhostslave). I can not figure out how to connect and mange the input/output ports in its project and in which way I can map them to physical USB connector's pins.
Precisely, I need a project that works with this IP Core and has been implemented on one of Altera/Xilinx's FPGA boards.
Is there any one that could help me?
Thanks in advance,
SHM